The present invention relates, in general, to electrical circuits, and more particularly, to a novel input buffer having sleep mode and bus hold for providing low static and dynamic power dissipation.
In the past, a variety of circuit configurations have been utilized to provide complementary metal oxide semiconductor (CMOS) circuits which are capable of accepting transistor-transistor logic (TTL) voltage levels. The semiconductor industry has also combined CMOS with bipolar to form BICMOS circuits having TTL compatible inputs. One notable disadvantage of most, if not all, such prior circuits is the amount of power dissipated by the circuits input stage. The voltage value of a TTL signal generally varies over a large range, and often drops to a level that is insufficient to disable the prior circuits input transistors. When this occurs, excessive power is dissipated in the form of leakage current flowing through these input transistors.
There have been attempts to minimize the static power dissipation of an input stage. For example, a circuit for lowering the operating potential of the input transistors of the circuit and then restoring the voltage level at the output of the circuit is fully described in U.S. patent application having U.S. Pat. No. 5,276,362 and issue date of Jan. 4, 1994. Although the circuit minimizes static power dissipation, it does not, however, minimize the dynamic power dissipation nor does it provide a sleep mode or a bus hold function;
Accordingly, it is desirable to provide a circuit that has an input which operates with a TTL input signal, that has low static and dynamic power dissipation, and that has the capability of operating in a sleep mode and a bus hold function.